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Setup Slack Calculator

Enter clock period, data path delay, setup time and clock skew to get the setup slack and max frequency.

How it is calculated

The tool checks the setup condition of one path between two flip-flops, with all times in nanoseconds. slack = T + skew − tdata − tsetup, where T is the clock period, skew is the capture clock's arrival minus the launch clock's (positive skew gives extra time, negative skew takes it away), tdata is the delay from clock edge to data arrival and tsetup is the flip-flop's setup time. Zero or more is a pass; negative means the path is too slow. The second line gives the limit imposed by this path: Tmin = tdata + tsetup − skew and fmax = 1000 / Tmin in MHz. It does not depend on the period you typed, and it shows a dash if Tmin is zero or negative. Period must be above zero, delay and setup cannot be negative, and skew defaults to 0. Hold slack is not calculated here.

Worked example

Clock period 8 ns, data path delay 6.2 ns, setup time 0.9 ns, skew +0.4 ns. Slack = 8 + 0.4 − 6.2 − 0.9 = 1.30 ns, positive, so setup is met with 1.3 ns to spare. Minimum period: 6.2 + 0.9 − 0.4 = 6.7 ns, so fmax = 1000 / 6.7 = 149.25 MHz. At the 8 ns period (125 MHz) the path has room; the clock could be sped up until the period falls to 6.7 ns. With skew of −0.4 ns instead, slack drops to 0.50 ns and fmax to 133.33 MHz.

Try this example →

Common mistakes

  • Getting the sign of skew wrong. Here positive skew means the capture clock arrives later and helps setup; if your tool reports skew the other way round, enter it with the opposite sign.
  • Mixing units: the fields are in nanoseconds. A 100 MHz clock is a 10 ns period, and typing 100 or 0.01 would give nonsense.
  • Leaving out the clock-to-output delay of the launching flip-flop. The data delay should be the whole delay from clock edge to data arriving at the capture pin, or the slack looks better than it is.
  • Reading fmax as the speed of the whole chip. It comes from this one path only; the real limit is set by the path with the least slack.
  • Treating positive slack as a pass for hold. A hold violation does not depend on the period, and this tool does not check it.

About this calculator

This calculator computes the setup timing slack of a synchronous digital path between two flip-flops, one of the two checks (alongside hold slack) that make up static timing analysis (STA). The formula is Clock Period + Clock Skew − Data Path Delay − Setup Time: positive slack means the data arrives with margin to spare before the next clock edge; negative slack means the path is too slow and the circuit will fail at that clock frequency.

Digital and FPGA/ASIC designers use setup slack analysis to find the critical path in a chip and to determine the maximum safe clock frequency, which is simply the inverse of the minimum clock period that keeps slack non-negative across every path.

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